The present invention relates to a contact structure for a semiconductor device, and more particularly to a contact structure having a side contact formed on the side face of an impurity-doped region.
An integrated circuit is created by many circuit patterns on a single-crystal semiconductor substrate. The semiconductor substrate is divided into active regions and isolation regions, both electrically and structurally, by a local oxidation of silicon (LOCOS) method or a trench method. Here, interconnection technology is used to connect isolated devices. To connect the isolated devices, a material having high conductivity and thin-film properties, e.g., polysilicon or aluminum, is used.
Meanwhile, a contact for the interconnection is formed as follows. First, an oxide film is formed on a semiconductor substrate by a conventional method such as thermal oxidation. Next, the oxide film is patterned to form an oxide film pattern having an opening. Then, a conductive material is deposited over the entire surface of the semiconductor substrate having the opening. Thus, a contact region is formed on the opening by the deposited conductive material, and the substrate and conductive material are then interconnected. Such an interconnection can be classified as a semiconductor substrate-to-metal contact (made of, for example, aluminum) or a semiconductor substrate-to-polysilicon contact.
The above interconnection technology is disclosed in Silicon Processing for the VLSI Era (Vol.2, pg. 160-162), which describes a buried contact structure and a butting contact structure as means for interconnection. FIG. 1 is a cross-sectional view showing the disclosed buried contact structure.
Referring to FIG. 1, a buried contact structure is comprised of a semiconductor substrate 1, a first oxide layer 2 for defining a contact region 6, a trench isolation region 3 for isolating an active region, a first conductive layer 4 for connecting with an impurity-doped region 5, a second conductive layer 4a closely spaced with respect to the first conductive layer 4. Here, when the first conductive layer 4, e.g., a polysilicon layer, and the impurity-doped region 5 are connected in the buried contact structure, the first conductive layer 4 is directly connected to the impurity-doped region 5, which thus forms contact region 6.
Also, a cross-sectional view of the butting contact structure disclosed in "Silicon Processing for the VLSI Era." is shown in FIG. 2. Here, a butting contact structure is comprised of a semiconductor substrate 1, a first oxide layer 2 for defining a contact region 6, a trench isolation region 3 for isolating an active region, a first conductive layer 4 for connecting an impurity-doped region 5 formed on the semiconductor substrate 1, a second oxide layer 7 formed on the first conductive layer 4, a second conductive layer 8 for connecting the first conductive layer 4 (e.g., a polysilicon layer) and the impurity-doped region 5, and a third conductive layer 8a closely spaced with respect to the second conductive layer 8. Here, when the first conductive layer 4 and the impurity-doped region 5 are connected in the butting contact structure, first conductive layer 4 is connected to impurity-doped region 5 through second conductive layer 8, e.g., an aluminum or polysilicon layer, and thus forms contact region 6.
However, the buried contact structure and the butting contact structure as described above have certain problems. Foremost among these is the difficulty in reducing the size of each isolated device so as to further integrate a circuit formed by these devices. Accordingly, the width and area of the isolation region formed between devices and the length of the interconnection of a contact structure must all be reduced.
In FIGS. 1 and 2, the first conductive layer 4 of FIG. 1 and the second conductive layer 8 of FIG. 2 are formed on and connected to the impurity-doped region 5 in a planar manner, such that a sufficient length "b" is always present.
Also, as shown in FIG. 1, the first conductive layer 4 must have a predetermined length or region, in order to connect the impurity-doped region 5. Accordingly, when second conductive layer 4a is closely spaced with respect to the first conductive layer 4, a sufficient length "a" is also needed to isolate devices. Likewise, when the third conductive layer 8a is closely spaced with respect to the second conductive layer 8, as shown in FIG. 2, length "a" is needed to isolate devices.
As described above, when the conductive layer, i.e., layers 4 and 4a of FIG. 1 and layers 8 and 8a of FIG. 2, are connected to the impurity-doped region 5 in a planar manner, lengths "a" and "b" are inevitable. Thus, it is difficult to reduce the unit cell area of a semiconductor device.